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Content Provider | IEEE Xplore Digital Library |
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Author | Tingting Yu Aijiao Cui Mengyang Li Ivanov, A. |
Copyright Year | 2015 |
Description | Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of British Columbia, Vancouver, BC, Canada (Ivanov, A.) || Sch. of Electron. & Inf. Eng., Harbin Inst. of Technol., Shenzhen, China (Tingting Yu; Aijiao Cui; Mengyang Li) |
Abstract | Scan design is regarded as the best design-for-testability (DfT) discipline. High test data volume and long test time are always two major concerns that our work here addresses. Here we combine a test data compression technique and broadcast-based decompressor architecture to relieve these problems. We propose a new decompressor architecture with bidirectional shift register as a source chain to broadcast compressed data into parallel scan chains. It enables one more broadcasting mode which leads to a higher broadcast ratio. We also propose a heuristic method to order the scan cells in each sub scan chain to improve the broadcast ratio so as to reduce the test data and test time. We apply our method on several benchmark circuits and the experimental results show that our method can reduce test data volume by 22.8% and shorten test application time by 19.5% on average with low area overhead in comparison to other state-of-the-art approaches. |
Starting Page | 641 |
Ending Page | 644 |
File Size | 655045 |
Page Count | 4 |
File Format | |
ISBN | 9781479983919 |
DOI | 10.1109/ISCAS.2015.7168715 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2015-05-24 |
Publisher Place | Portugal |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Shift registers Clocks Broadcasting Computer architecture Design methodology Multiplexing test application time broadcast ratio decompressor paralll chain test data volume |
Content Type | Text |
Resource Type | Article |
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