NDLI: Wide linear range voltage-controlled delay unit for time-mode signal processing

Content Provider	IEEE Xplore Digital Library
Author	Ziabakhsh, S. Gagnon, G. Roberts, G.W.
Copyright Year	2015
Description	Author affiliation: Ecole de Technol. Super., Univ. du Q, Montreal, QC, Canada (Ziabakhsh, S.; Gagnon, G.) \|\| Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, QC, Canada (Roberts, G.W.)
Abstract	A voltage-controlled delay unit (VCDU) for low-voltage time-mode signal processing is presented in this paper. The proposed VCDU uses a signal conditioning circuit to achieve wider-range and higher linearity than state-of-the-art VCDUs. Circuit-level simulations in 0.18μm CMOS process show a linearity error of less than ± 0.2% for a 0.15 V to 1 V input range. The proposed VCDU consumes 315 μW from a 1.8 V supply at its maximum sampling frequency of 500 MHz. The proposed VCDU is validated in a first-order time-mode ΔΣ modulator application. Circuit-level simulation results of the ΔΣ modulator show a peak SNDR of 58 dB when clocked at 140 MHz with a 400 kHz bandwidth.
Starting Page	1826
Ending Page	1829
File Size	648669
Page Count	4
File Format	PDF
ISBN	9781479983919
DOI	10.1109/ISCAS.2015.7169011
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Linearity Transistors Capacitors Frequency modulation CMOS integrated circuits
Content Type	Text
Resource Type	Article

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Wide linear range voltage-controlled delay unit for time-mode signal processing