NDLI: A new highly-linear highly-sensitive differential voltage-to-time converter circuit in CMOS 65nm technology

Content Provider	IEEE Xplore Digital Library
Author	El-Bayoumi, A. Mostafa, H. Soliman, A.M.
Copyright Year	2015
Description	Author affiliation: Electron. & Electr. Commun. Eng. Dept., Cairo Univ., Cairo, Egypt (El-Bayoumi, A.; Mostafa, H.; Soliman, A.M.)
Abstract	Time-Based Analog-to-Digital Converter (ADC), at scaled CMOS technology, plays a major role in designing Software Defined Radio (SDR) receivers as it manifests higher speed and lower power than conventional ADCs. Time-Based ADC includes a Voltage-to-Time converter (VTC) which converts the input voltage into a pulse delay, and a Time-to-Digital Converter which converts the pulse delay into a digital word. In this paper, a novel design of a differential VTC circuit is proposed which reports wider dynamic range and higher sensitivity than previously published VTC circuits in TSMC 65nm CMOS technology, with a supply voltage of 1.2V. This new VTC circuit operates with no sample and hold circuit for analog input frequencies up to 2.5 GHz with a linearity error of 3%.
Starting Page	1262
Ending Page	1265
File Size	528931
Page Count	4
File Format	PDF
ISBN	9781479983919
DOI	10.1109/ISCAS.2015.7168870
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS integrated circuits Linearity Delays Dynamic range Sensitivity CMOS technology Analog-digital conversion
Content Type	Text
Resource Type	Article

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