NDLI: Delay window blind oversampling clock and data recovery algorithm with wide tracking range

Content Provider	IEEE Xplore Digital Library
Author	Bartley, T. Tanaka, S. Nonomura, Y. Nakayama, T. Muroyama, M.
Copyright Year	2015
Description	Author affiliation: Partner Robot Div., Toyota Motor Corp., Toyota, Japan (Nakayama, T.) \|\| Microsyst. Integration Center, Tohoku Univ., Sendai, Japan (Bartley, T.; Tanaka, S.; Muroyama, M.) \|\| Toyota Central R&D Labs., Toyota Central R&D Labs., Inc., Nagakute, Japan (Nonomura, Y.)
Abstract	A new blind oversampling clock and data recovery (BO-CDR) algorithm is proposed. It has high tolerance to low-frequency jitter (14.8 unit intervals at 10 kHz, measured at 640 Mbps) and is suitable for systems where the receiver clock has high drift with respect to the transmission. The algorithm is capable of recovering data over a wide tracking range or when the precise oversampling rate (β) is not known a priori, for any real-valued oversampling rate, β ≥ 3, making this BO-CDR algorithm the first to not require integer-valued β. To demonstrate the utility of the algorithm, two implementations are designed and evaluated. The first is used in a low-power, low-data rate sensor node IC with a low-performance single phase clock source. The second is a high-speed receiver with a multiple phase clock source implemented on FPGA. The CDR core consists of just 47 logic cells and 19 registers and has an estimated power consumption of 0.70 mW at 640 Mbps. The properties of this CDR algorithm make it appropriate for a wide range of applications in serial communication.
Starting Page	1598
Ending Page	1601
File Size	480335
Page Count	4
File Format	PDF
ISBN	9781479983919
DOI	10.1109/ISCAS.2015.7168954
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Jitter Algorithm design and analysis Receivers Image edge detection Delays Bit error rate
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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