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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Siemon, A. Menzel, S. Chattopadhyay, A. Waser, R. Linn, E. |
| Copyright Year | 2015 |
| Description | Author affiliation: Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore, Singapore (Chattopadhyay, A.) || Inst. fur Werkstoffe der Elektrotechnik II (IWE II), RWTH Aachen Univ., Aachen, Germany (Siemon, A.; Waser, R.; Linn, E.) || Peter Grunberg Inst. 7 (PGI-7), Forschungszentrum Julich GmbH, Jülich, Germany (Menzel, S.) |
| Abstract | Memristive devices enable non-volatile data storage and in-memory computing capabilities. By using stateful logic approaches, hybrid CMOS nano-crossbar arrays offer additional functionalities such as arithmetic operations. To enable storage and computing on large-scale arrays, parasitic current paths within the array must be avoided. Therefore, for example, a complementary resistive switch (1CRS) or a bipolar rectifying element (`selector') in series to a resistive switching device (1S1R) is required at each cross-point junction to suppress low-ohmic sneak paths. In this work 1S1R arrays are considered. First, the in-memory adder concept, initially developed for CRS arrays, is adjusted for a 1S1R array. After that an optimized design is presented and verified by means of memristive simulations. Third, the energy consumption of both concepts is evaluated as a function of array size, and the delay of memristive adder designs are compared quantitatively. |
| Starting Page | 1338 |
| Ending Page | 1341 |
| File Size | 534748 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479983919 |
| DOI | 10.1109/ISCAS.2015.7168889 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-05-24 |
| Publisher Place | Portugal |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Adders Switches Energy consumption CMOS integrated circuits Junctions Delays Computer architecture adder Memristor memristive device resistive switching complementary resistive switch sequential logic |
| Content Type | Text |
| Resource Type | Article |
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