NDLI: Hardware design and FPGA implementation for road plane extraction based on V-disparity approach

Content Provider	IEEE Xplore Digital Library
Author	Benacer, I. Hamissi, A. Khouas, A.
Copyright Year	2015
Description	Author affiliation: LIMOSE Lab., Univ. M'Hamed Bougara of Boumerdes, Boumerdès, Algeria (Khouas, A.) \|\| LSN Lab., Ecole Militaire Polytech., Bordj El Bahri, Algeria (Benacer, I.; Hamissi, A.)
Abstract	Accurate and real-time free space and obstacles detection is a task of great interest to the navigation of mobile robots, and the integration to existing vehicle's safety systems. This paper presents a novel approach for road plane extraction, free space and obstacles discrimination using stereovision. The estimated road profile from V-disparity images allows robust extraction of the road features from pixels classification of the disparity map. The proposed hardware architecture combines parallel processing with dedicated and optimized modules to reduce logic resource utilization, and accelerate processing time. This architecture is implemented on Cyclone IV E FPGA based prototyping board, and tested using real stereoscopic images of different environments. Experimental results demonstrate the efficiency and accuracy of the proposed method. The implemented system can treat up to 490 and 122 frames/s for stereoscopic images of 320×240 and 640×480 pixels respectively.
Starting Page	2053
Ending Page	2056
File Size	1042102
Page Count	4
File Format	PDF
ISBN	9781479983919
DOI	10.1109/ISCAS.2015.7169081
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Roads Estimation Field programmable gate arrays Hardware Computer architecture Real-time systems Mobile robots Free space estimation Stereovision V-disparity map Road plane extraction
Content Type	Text
Resource Type	Article

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Hardware design and FPGA implementation for road plane extraction based on V-disparity approach

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