NDLI: Design of high-temperature SRAM for reliable operation beyond 250°C

Content Provider	IEEE Xplore Digital Library
Author	Cojbasic, R. Leblebici, Y.
Copyright Year	2015
Description	Author affiliation: Microelectron. Syst. Lab. (LSM), Swiss Fed. Inst. of Technol. Lausanne (EPFL), Lausanne, Switzerland (Cojbasic, R.; Leblebici, Y.)
Abstract	In this paper, we analyze the 6T SRAM cell failures caused by temperature and supply voltage variations, and we explore the design of robust SRAM cells for high temperature operation. This integral SRAM reliability study is performed using 180nm SOI CMOS process transistor models. Three different operation regions are identified based on the temperature and supply voltage impact on failure rates. We show that in the super-threshold operation region failure rates increase with elevated temperatures while the opposite is true in the sub-threshold operation regions. We also provide physical interpretation of particularly interesting near-threshold operation region that demonstrated extremely high reliability and low failure rates. Further, we present reliability improvements of the 6T SRAM cell which lead to the fully-digital Latch based design. Silicon measurements demonstrate reliable, state-of-the-art, SRAM operation at 275°C $(f_{MAX}$ = 10MHz, $P_{TOT}$ = 400mW), that is by far the highest reported operating temperature for digital on-chip SRAM module.
Starting Page	2545
Ending Page	2548
File Size	1275761
Page Count	4
File Format	PDF
ISBN	9781479983919
DOI	10.1109/ISCAS.2015.7169204
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SRAM cells Latches Temperature measurement Power demand Integrated circuit reliability
Content Type	Text
Resource Type	Article

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