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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhenqi Wei Peilin Liu Rongdi Sun Rendong Ying |
| Copyright Year | 2015 |
| Description | Author affiliation: Sch. of Electron., Inf. & Electr. Eng., Shanghai Jiao Tong Univ., Shanghai, China (Zhenqi Wei; Peilin Liu; Rongdi Sun; Rendong Ying) |
| Abstract | As one of the mostly used synchronization schemes in parallel programming on multi-core processors, barrier synchronization has been extensively studied in former research works. In conventional master-slave barrier or tree barrier, usually one centric core is selected to collect barrier arriving messages and to broadcast barrier releasing messages. Unfortunately the barrier core sometimes is deviated from the center location and may lead to worse synchronization efficiency. We propose a hybrid tree-based all-to-all (TAB) barrier for NoC-based many-core processors to relieve performance degradation caused by the off-centered barrier core. Performance of TAB barrier is compared to canonical algorithms and former solution, and almost 20% time is saved during off-centered scenarios with marginal area and power overhead. |
| Starting Page | 409 |
| Ending Page | 412 |
| File Size | 575117 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479983919 |
| DOI | 10.1109/ISCAS.2015.7168657 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-05-24 |
| Publisher Place | Portugal |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Synchronization Program processors System-on-chip Merging Hardware Multicast communication Multicore processing Synchronization Controller NoC Barrier Synchronization Critical Path |
| Content Type | Text |
| Resource Type | Article |
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