NDLI: A hardware based low temperature solution for VLSI testing using decompressor side masking

Content Provider	IEEE Xplore Digital Library
Author	Dutta, A. Kundu, S. Chattopadhyay, S. Kumar Das, B.
Copyright Year	2015
Description	Author affiliation: Dept. of E&ECE, Indian Inst. of Technol. Kharagpur, Kharagpur, India (Dutta, A.; Chattopadhyay, S.; Kumar Das, B.) \|\| Synopsys India Pvt. Ltd., India (Kundu, S.)
Abstract	The temperature of a block (a region in the chip) depends on both heat generation (caused by power consumption) and heat dissipation among neighbors. Power aware test solutions targeting low power consumption during testing, may not produce an acceptable thermal aware solution. In this paper, a hardware based solution using an AND-OR block between the decompressor and each scan chain, has been utilized to deactivate some scan chains during loading to reduce peak temperature during testing. The proposed schemes require negligible hardware overhead and do not require any special patterns. Experimental results of our proposed approach on ISCAS'89 and ITC'99 benchmark circuits show a good reduction in peak temperature.
Starting Page	637
Ending Page	640
File Size	550397
Page Count	4
File Format	PDF
ISBN	9781479983919
DOI	10.1109/ISCAS.2015.7168714
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Testing Fault detection Hardware Very large scale integration Heating Flip-flops Scan Cell Clustering HotSpot AND-OR block Decompressor side masking
Content Type	Text
Resource Type	Article

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