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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Haibo Yu Guoqiang Bai |
| Copyright Year | 2015 |
| Description | Author affiliation: Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China (Haibo Yu) || Dept. of Microeletronics & Nanoelectron., Tsinghua Univ., Beijing, China (Guoqiang Bai) |
| Abstract | In this paper, we propose an efficient method for integer factorization and it can be a good solution to sieving part of General Number Field Sieve. The mid-size integer factorization module adopts highly parallel structure to save operation time to a great extent. The algorithm used in the factorization module is another highlight that only involves the basic arithmetic operations, which makes for hardware implementation. The major goal of the proposed method is to optimize performance on the aspects of operation time, implemented hardware algorithm and storage space. Additionally, the proposed implementation has absolute advantage at operation speed based on FPGAs, which is of crucial importance for large integer factorization. |
| Starting Page | 73 |
| Ending Page | 76 |
| File Size | 1051343 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479983919 |
| DOI | 10.1109/ISCAS.2015.7168573 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-05-24 |
| Publisher Place | Portugal |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware Field programmable gate arrays Electronic countermeasures Standards Clocks Algorithm design and analysis Digital signal processing parallel structure general number field sieve (GNFS) sieving part mid-size integer prime factor |
| Content Type | Text |
| Resource Type | Article |
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