NDLI: Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes

Content Provider	IEEE Xplore Digital Library
Author	Beigne, E. Clermidy, F. Lattard, D. Miro-Panades, I. Thonnart, Y. Vivet, P.
Copyright Year	2015
Description	Author affiliation: CEA LETI Minatec Campus, Grenoble, France (Beigne, E.; Clermidy, F.; Lattard, D.; Miro-Panades, I.; Thonnart, Y.; Vivet, P.)
Abstract	In this paper we propose to give an overview of fine-grain design techniques we demontrated past years in our lab for power reduction in complex SoCs. Those works are based on Globally Asynchronous and Locally Synchronous systems in which each IP is an independent voltage and frequency domain. After having proposed some simple DFS architectures based on GALS architectures in 130nm technology, we extended our works to fine-grain Dynamic Voltage and Frequency Scaling architectures to reduce dynamic and static power reduction at 65 nm node. Furthermore, considering 32 nm deep submicron technologies, we demonstrated an Adaptive Voltage and Frequency architecture to compensate for in-die PVT variations. Area overhead and power reduction results are discussed all along the paper.
Starting Page	1550
Ending Page	1553
File Size	584767
Page Count	4
File Format	PDF
ISBN	9781479983919
DOI	10.1109/ISCAS.2015.7168942
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Nickel Power demand OFDM System-on-chip IP networks Computer architecture Random access memory
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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