NDLI: Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design

Content Provider	IEEE Xplore Digital Library
Author	Zuloaga, S. Rui Liu Pai-Yu Chen Shimeng Yu
Copyright Year	2015
Description	Author affiliation: Sch. of Electr., Comput., & Energy Eng., Arizona State Univ., Tempe, AZ, USA (Zuloaga, S.; Rui Liu; Pai-Yu Chen; Shimeng Yu)
Abstract	The resistive random access memory (RRAM) technology is a promising candidate for the replacement of NAND FLASH at ultra-scaled nodes. In this work, the scalability of a 2-layer RRAM cross-point array architecture is explored towards the 10 nm node. Device-circuit co-design methodologies are employed to optimize the array architecture. The impact of sneak paths, IR drop along the wire interconnect and RRAM device characteristics are investigated by HSPICE simulations and the memory array organization and partition are optimized by NVSim simulations. It is found that increasing the I-V nonlinearity of a memory cell by adding a cell selector helps maintain the write voltage margin at scaled nodes. With the scaling, the maximum sub-array size decreases due to the IR drop constraint thus the memory architecture evolves to a finer granularity. At the 10 nm node, by hiding a portion of the peripheral circuitry underneath the memory array, a 2-layer RRAM bank is projected to achieve ultra-high density ~3.43 $Gb/mm^{2},$ and can enable fast write bandwith ~ 300 MB/s and read bandwidth ~1 GB/s.
Starting Page	193
Ending Page	196
File Size	1263815
Page Count	4
File Format	PDF
ISBN	9781479983919
DOI	10.1109/ISCAS.2015.7168603
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Arrays Microprocessors Bandwidth Integrated circuit modeling Flash memories Integrated circuit interconnections scaling resistive memory RRAM ReRAM cross-point array memory architecture
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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