NDLI: XOR-decomposition principle and its use to build a glitch-free maximum-speed arbitrary binary waveform generator and deglitcher

Content Provider	IEEE Xplore Digital Library
Author	Pedroni, V.A.
Copyright Year	2015
Description	Author affiliation: Fed. Technol. Univ. of Parana State, Curitiba, Brazil (Pedroni, V.A.)
Abstract	Arbitrary binary waveforms are needed for chip testing and for operating complexly-controlled devices. Such signals are required to be glitch-free and might have to be as fast as the fastest clock available, thus with transitions coinciding with both positive and negative clock edges, which prevents the use of conventional (by means of D-type flip-flops) deglitching of the generated signals. This paper introduces the XOR-decomposition principle, which allows any binary waveform to be decomposed into two other waveforms, each with half the frequency of the original (decomposed) signal, hence with transitions at only one of the clock edges, which then makes the use of conventional deglitching possible. This principle is used to build an inexpensive, glitch-free, maximum-speed, arbitrary binary waveform generator. It is also extended subsequently to build an inexpensive deglitcher for any max-speed binary waveform. Both solutions are standard (application-independent), with proper time predictability, suited for both VLSI- and FPGA-based implementations. Experimental results from FPGA implementations using VHDL are also reported.
Starting Page	1834
Ending Page	1837
File Size	416610
Page Count	4
File Format	PDF
ISBN	9781479983919
DOI	10.1109/ISCAS.2015.7169013
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Delays Table lookup Signal generators Field programmable gate arrays Standards Multiplexing deglitcher XOR decomposition binary waveform arbitrary waveform generator glitch free
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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