NDLI: Parallel pipelining configurable multi-port memory controller for multimedia applications

Content Provider	IEEE Xplore Digital Library
Author	Xuan-Thuan Nguyen Hong-Thu Nguyen Cong-Kha Pham
Copyright Year	2015
Description	Author affiliation: Dept. of Eng. Sci., Univ. of Electro-Commun., Chofu, Japan (Xuan-Thuan Nguyen; Hong-Thu Nguyen; Cong-Kha Pham)
Abstract	Despite many significant improvements of processors up to now, the off-chip memory performance has still lagged far behind. The high-performance memory controller, therefore, has become the key to success. In this paper, a parallel pipelining configurable multi-port memory controller is proposed to not only exploit the external memory bandwidth effectively, but also provide the flexibility in use and the independence from other system architectures. The proposed architecture is composed of multi-clock multi-data-width buffers to speed up the transactions, embedded memory to store the configuration, and priority scheme arbiter to schedule all access. The design, then, is evaluated in a low-cost low-power Altera Cyclone V FPGA with 1 GB DDR3 external memory. The experimental results demonstrate that the proposed controller can support up to 32 concurrent connections with various clocks and data width, and achieve approximately 82% and 87% of theory peak bandwidth in write and read process, respectively.
Starting Page	2908
Ending Page	2911
File Size	608414
Page Count	4
File Format	PDF
ISBN	9781479983919
DOI	10.1109/ISCAS.2015.7169295
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bandwidth Clocks Hardware Cyclones Streaming media Pipeline processing Field programmable gate arrays
Content Type	Text
Resource Type	Article

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