NDLI: 180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance

Content Provider	IEEE Xplore Digital Library
Author	Yuequan Liu Yuan Wang Song Jia Xing Zhang
Copyright Year	2015
Description	Author affiliation: Key Lab. of Microelectron. Devices & Circuits (MoE), Peking Univ., Beijing, China (Yuequan Liu; Yuan Wang; Song Jia; Xing Zhang)
Abstract	A wide range delay-locked loop (DLL) based clock and data recovery (CDR) circuit including coarse and fine tune blocks is proposed in this paper. The coarse tune block adopts a time to digital converter and digital control delay line to widen the frequency capture range, reduce locking time and prevent the false locking problem. In the fine tune block, a novel phase detector combines the tasks of sampling and charge-pump using half rate clock. Starting-control circuit can ensure CDR takes full use of the delay range provided by voltage control delay line. Moreover, a fully analog DLL technique is applied to exploit the benefits of low skew and jitter performance. The simulation result shows the proposed CDR can cover a wide frequency range from 180.5Mbps to 8Gbps, while the peak-to-peak jitter of recovery clock is 2.7ps at 200Mbps and 1.06ps at 8Gbps. Fabricated in a 65nm CMOS process, this design dissipates 9.9mW and 22.9mW respectively at 200 Mbps and 8Gbps from a 1.2 V supply.
Starting Page	1394
Ending Page	1397
File Size	792061
Page Count	4
File Format	PDF
ISBN	9781479983919
DOI	10.1109/ISCAS.2015.7168903
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Delays Jitter Partial discharges Tuning Delay lines Voltage control time-to-digital converter (TDC) Clock and data recovery (CDR) wide-range delay-locked loop (DLL) low jitter
Content Type	Text
Resource Type	Article

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