NDLI: Enabling highly energy efficient WSN through PLL-free, fast wakeup radios

Content Provider	IEEE Xplore Digital Library
Author	Thirunarayanan, R. Ruffieux, D. Enz, C.
Copyright Year	2015
Description	Author affiliation: EPFL, Neuchatel, Switzerland (Thirunarayanan, R.; Enz, C.) \|\| CSEM, Neuchatel, Switzerland (Ruffieux, D.)
Abstract	Energy wasted during the wake-up of radios significantly degrades the efficiency of duty-cycled Wireless Sensor Networks (WSN). The major contributor to this energy wastage is the PLL-based frequency synthesizer which has a long wakeup time. Furthermore, the rate of duty cycling in these radios is also constrained by the PLL which imposes an upper limit on the maximum data rate that can be achieved by the radio. In order to improve upon both these bottlenecks, this paper presents an overview of highly agile, PLL-free radios based on FBAR DCOs. These synthesizers have the advantage of a 5μs wakeup, thereby reducing the energy wastage. In addition, they also support high-data rates (upto 16 Mbps) thereby increasing the rate of duty cycling which also improves the energy efficiency. The extremely low phase noise of the FBAR is an added advantage that has been leveraged to provide a low power channel selection filter for a sub-sampling receiver architecture.
Starting Page	2573
Ending Page	2576
File Size	1644171
Page Count	4
File Format	PDF
ISBN	9781479983919
DOI	10.1109/ISCAS.2015.7169211
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Film bulk acoustic resonators Frequency shift keying Computer architecture Tuning Receivers Mixers Microprocessors fast wakeup WSN FBAR PLL-free Radios
Content Type	Text
Resource Type	Article

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