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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Eunho Yang Kyongsu Lee Jin-Ku Kang |
| Copyright Year | 2015 |
| Description | Author affiliation: Dept. of Electron. Eng., Inha Univ., Incheon, South Korea (Eunho Yang; Kyongsu Lee; Jin-Ku Kang) |
| Abstract | This paper presents a 120-to-520Mb/s clock and data recovery (CDR) circuit that utilizes pulse width modulation (PWM) signaling scheme. Compared to the conventional approach, the proposed retiming scheme improves sampling margin over 200%, which results in lower BER. The proposed idea has been simulated in a 65nm CMOS technology. The post layout simulation result has shown that recovered clock and data have 3.42ps and 7.55ps rms jitter at 500Mb/s data rate. The CDR circuit consumes 1.97mW (1.2V supply) at 500Mb/s of MIPI M-PHY signaling format. |
| Starting Page | 345 |
| Ending Page | 348 |
| File Size | 840272 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479983919 |
| DOI | 10.1109/ISCAS.2015.7168641 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-05-24 |
| Publisher Place | Portugal |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Pulse width modulation Clocks Jitter Flip-flops Voltage-controlled oscillators Logic gates Phase locked loops MIPI M-PHY Pulse width modulation (PWM) low voltage differential signal (LVDS) clock and data recovery (CDR) |
| Content Type | Text |
| Resource Type | Article |
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