NDLI: Analysis and optimization for dynamic read stability in 28nm SRAM bitcells

Content Provider	IEEE Xplore Digital Library
Author	Elthakeb, A.T. Haine, T. Flandre, D. Ismail, Y. Abd Elhamid, H. Bol, D.
Copyright Year	2015
Description	Author affiliation: Center for Nano-Electron. & Devices (CND), American Univ. in Cairo (AUC), Cairo, Egypt (Elthakeb, A.T.; Ismail, Y.; Abd Elhamid, H.) \|\| ICTEAM Inst., Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium (Haine, T.; Flandre, D.; Bol, D.)
Abstract	The importance of the dynamic analysis for SRAM operation increases as a result of shrinking access cycle time, voltage scaling and increased process variations. In this paper, quantitative study of the dynamic read noise margin (DNM) is introduced showing the evolution from the static read noise margin (SNM) to DNM through cumulative dynamic effects in 28nm FDSOI. The impact of parasitic capacitances on the DNM is further analyzed. Finally, we show that by sizing for a 150-mV DNM instead of a 150-mV SNM and by inserting two 0.5fF extra caps in the bitcell allows reducing the pull-down NMOS width by a factor 3.5×.
Starting Page	1414
Ending Page	1417
File Size	532946
Page Count	4
File Format	PDF
ISBN	9781479983919
DOI	10.1109/ISCAS.2015.7168908
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitance Stability analysis Random access memory Noise Circuit stability Couplings Transient analysis FD SOI Dynamic behavior 6T SRAM Read Noise Margin parasitic capacitances Cell sizing
Content Type	Text
Resource Type	Article

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