NDLI: FPGA implementation for stereo matching algorithm

Content Provider	IEEE Xplore Digital Library
Author	Baha, N. Touzene, H. Larabi, S.
Copyright Year	2013
Description	Author affiliation: Instrum. Dept., Univ. of Sci. & Technol. USTHB, Algiers, Algeria (Touzene, H.) \|\| Comput. Sci. Dept., Univ. of Sci. & Technol., Algiers, Algeria (Baha, N.; Larabi, S.)
Abstract	To reach a real-time stereo vision in embedded systems, we propose in this paper, the adaptation and optimization of the well-known Disparity Space Image (DSI) on a single FPGA(Field programmable gate Arrays) that is designed for high efficiency when realized in hardware. An initial disparity map was calculated using the DSI structure and then a median filter was applied to smooth the disparity map. Many methods reported in the literature are mainly restricted to implement the SAD algorithm (Sum of Absolute Differences) on an FPGA. An evaluation of our method is done by comparing the obtained results of our method with a very fast and well-known sum of absolute differences algorithm using hardware-based implementations.
Starting Page	448
Ending Page	454
File Size	1411609
Page Count	7
File Format	PDF
ISBN	9780989319300
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-07
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	The Science and Information Organization
Subject Keyword	Occlusion Accuracy Image resolution FPGA Real-time Computer architecture DSI (Disparity Space Image) Hardware Real-time systems Stereo vision Field programmable gate arrays
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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