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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Malta, D. Gregory, C. Lueck, M. Temple, D. Krause, M. Altmann, F. Petzold, M. Weatherspoon, M. Miller, J. |
| Copyright Year | 2011 |
| Description | Author affiliation: RTI International, Research Triangle Park, NC, USA (Malta, D.; Gregory, C.; Lueck, M.; Temple, D.) || Fraunhofer Institute for Mechanics of Materials (IWM), Halle, Germany (Krause, M.; Altmann, F.; Petzold, M.) || Harris Corporation, Government Communications Systems Division, Melbourne, FL, USA (Weatherspoon, M.; Miller, J.) |
| Abstract | Successful implementation of 3D integration technology requires understanding of the unique yield and reliability issues associated with through-silicon vias (TSVs), with adequate design and process considerations to address these issues. This paper relates to the characterization of thermo-mechanical stress and reliability issues for Cu-filled TSVs designed for use in 3D Si interposers and 3D wafer-level packaging applications. The paper will describe a variety of methods for characterization of Cu TSV fill quality, microstructure, and thermally-induced TSV height increase known as “copper protrusion” or “copper pumping.” An X-ray imaging method was used for fast, nondestructive analysis of Cu TSV plating profiles and detection of trapped voids. In addition, a plasma focused ion beam (plasma-FIB) process was used to generate high quality cross sections of full TSVs, 50μm in diameter and 150μm depth. Imaging of TSVs by Ga FIB channeling contrast and electron backscattered diffraction (EBSD) provided information about Cu microstructure, including quantitative analysis of grain size. It was observed that TSVs exposed to elevated temperatures exhibited a substantial increase in grain size, which was associated with the Cu protrusion effect. This paper will also report the results of TSV integration with subsequent layers, with analysis of thermo-mechanical failures due to interactions between Cu TSVs and adjacent dielectric layers. The use of an anneal step to stabilize the plated Cu TSVs, prior to build-up of subsequent dielectric layers, will be described. |
| Starting Page | 1815 |
| Ending Page | 1821 |
| File Size | 2139928 |
| Page Count | 7 |
| File Format | |
| ISBN | 9781612844978 |
| ISSN | 05695503 |
| e-ISBN | 9781612844985 |
| e-ISBN | 9781612844961 |
| DOI | 10.1109/ECTC.2011.5898761 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-05-31 |
| Publisher Place | Florida, USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Through-silicon vias Copper Annealing Dielectrics Substrates Three dimensional displays Grain size |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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