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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhongping Bao Burrell, J. Keser, B. Yadav, P. Kalchuri, S. Zang, R. |
| Copyright Year | 2011 |
| Description | Author affiliation: Qualcomm Inc. 5775 Morehouse Drive, San Diego, CA 92121 (Zhongping Bao; Burrell, J.; Keser, B.; Yadav, P.; Kalchuri, S.; Zang, R.) |
| Abstract | Wafer Level Packaging (WLP) refers to the technology that integrated circuits are packaged at wafer level and after singulation such chips are then connected directly to the PCB through individual solder balls using standard SMT process [1,2,3,4]. WLP enables true chip size packages with other advantages including lower profile, lighter weight, better thermal and electrical performance, and lower cost. Since the devices are packaged at the wafer level, assembly of discrete chips, interconnects such as bumps or wire bonds, and substrates are eliminated. In this paper we carried out empirical and numerical studies of solder joint reliability under thermal cycling for ball-on-redistribution layer (RDL) type WLP. Test vehicles (TV) covering large range of die size as well die aspect ratio are designed and tested for board level reliability under thermal cycling. Large variations in bump layout and overall ball density are also considered in the TVs. Experimental setup monitors both corner and non-corner ball failures and reports the $1^{st}$ plus 1% failure. 3-D finite element modeling is performed to investigate the effects of die size, and ball pattern on board level solder joint reliability under thermal cycling. Hyperbolic sine law proposed in [5,11] is assumed for modeling solder creep behavior. Thermal fatigue life model presented in [6,7] is implemented here for establishing correlation between empirical data and simulation results. By including realistic boundary conditions and refined mesh in observed solder failure region, the simulation achieves excellent correlation and prediction compared to empirical data, within 12% error in terms of $1^{st}$ cycle to failure. The effect of die size, as well as die aspect ratio is examined. It is found that DNP shows a strong linear correlation to the metric, ISED — Inelastic Strain Energy Density, extracted in solder region from the numerical model. Since a power law between ISED and $1^{st}$ failure in cycles is assumed for life prediction, a similar empirical formula between die size and $1^{st}$ failure in cycles can then be defined based on modeling data. Effects of customized board and boundary conditions on solder joint reliability are also included. The paper is prepared to the best knowledge of authors and those statements do not necessarily reflect opinions of Qualcomm Inc or any other parties. Some data shared in this paper is normalized such that no commercial confidential information is published. |
| Starting Page | 761 |
| Ending Page | 766 |
| File Size | 929982 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781612844978 |
| ISSN | 05695503 |
| e-ISBN | 9781612844985 |
| e-ISBN | 9781612844961 |
| DOI | 10.1109/ECTC.2011.5898598 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-05-31 |
| Publisher Place | Florida, USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Reliability Soldering Numerical models Correlation Fatigue Vehicles Boundary conditions |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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