NDLI: Thermo-mechanical behavior of through silicon vias in a 3D integrated package with inter-chip microbumps

Content Provider	IEEE Xplore Digital Library
Author	Xi Liu Qiao Chen Sundaram, V. Simmons-Matthews, M. Wachtler, K.P. Tummala, R.R. Sitaraman, S.K.
Copyright Year	2011
Description	Author affiliation: School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332 (Sundaram, V.) \|\| The George W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332 (Xi Liu; Sitaraman, S.K.) \|\| School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, GA 30332 (Qiao Chen; Tummala, R.R.) \|\| Texas Instruments, Dallas, TX 75265 (Simmons-Matthews, M.; Wachtler, K.P.)
Abstract	Through-silicon via (TSV), being one of the key enabling technologies for 3D system integration, is being used to interconnect 3D vertically stacked devices, such as logic, memory, sensors, and actuators that are fabricated on separate wafers and then interconnected by either wafer-to-wafer or chip-to-wafer methods. However, thermo-mechanical analyses on TSVs are limited, and most of the existing studies focus on the thermo-mechanical analysis of TSVs in a freestanding wafer, rather than in an integrated package. In this paper, three-dimensional thermo-mechanical finite-element models have been built to analyze the stress/strain distribution in a 3D integrated package which contains stacked dice with TSVs, inter-chip microbumps, overmold, and underfilled solder bumps, and an organic substrate. Models show that the stresses in the TSV under packaging configuration could be generally lower than the stresses in the TSV in a free-standing wafer. Also, the models show that the high-strain region switches from TSV corners to microbumps.
Starting Page	1190
Ending Page	1195
File Size	1774549
Page Count	6
File Format	PDF
ISBN	9781612844978
ISSN	05695503
e-ISBN	9781612844985
e-ISBN	9781612844961
DOI	10.1109/ECTC.2011.5898661
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-31
Publisher Place	Florida, USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Through-silicon vias Stress Strain Copper Three dimensional displays Packaging Thermomechanical processes Thermo-Mechanical Stress Analysis Through Silicon Via 3D Packaging Finite-Element Modeling
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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