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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Che, F.X. Chai, T.C. Lim, S.P.S. Rajoo, R. Xiaowu Zhang |
| Copyright Year | 2011 |
| Description | Author affiliation: Institute of Microelectronics, A∗STAR (Agency for Science, Technology and Research), 11 Science Park Road, Science Park II, Singapore, 117685 (Che, F.X.; Chai, T.C.; Lim, S.P.S.; Rajoo, R.; Xiaowu Zhang) |
| Abstract | In this work, the reliability of a pyramidal shape 3-layer stacked TSV die package has been studied by experiments and finite element analysis (FEA). The originally designed microbumps are located peripherally around the edge of the die, which induces a concentrated bending force on the lower die when stacking the upper die. FEA simulation results show that such bump design induces large stress and deflection in the lower die during die stacking process. In this work, 3-point bend tests are conducted to determine the die strength. Actual die stacking experiments have been carried out and the results show that the bottom die cracks when stacking the middle die, and the bottom die cracks when stacking the top die even using a lower stacking force. Consistent results are achieved among FEA simulation, die strength bend test, and actual die stack experimental results. A new bump layout design has been optimized with some dummy bumps added on the central area of the die to directly support bending force induced by die stacking. The new design significantly reduces die stress and deflection. Eventually, a successful die stacking process is achieved even using a larger stacking force. The optimal bump layout design also leads to a lower package warpage in solder reflow process compared to the original bump layout design. |
| Starting Page | 1428 |
| Ending Page | 1435 |
| File Size | 1511389 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781612844978 |
| ISSN | 05695503 |
| e-ISBN | 9781612844985 |
| e-ISBN | 9781612844961 |
| DOI | 10.1109/ECTC.2011.5898699 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-05-31 |
| Publisher Place | Florida, USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Stacking Force Stress Layout Semiconductor device modeling Load modeling Simulation |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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