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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Woonseong Kwon Jaesik Lee Lee, V. Seetoh, J. Yenchen Yeo YeeMong Khoo Ranganathan, N. Keng Hwa Teo Shan Gao |
| Copyright Year | 2011 |
| Description | Author affiliation: Institute of Microelectronics, A∗STAR (Agency for Science, Technology and Research), 11, Science Park Road, Science Park II, Singapore, 117685 (Woonseong Kwon; Jaesik Lee; Lee, V.; Seetoh, J.; Yenchen Yeo; YeeMong Khoo; Ranganathan, N.; Keng Hwa Teo; Shan Gao) |
| Abstract | The building blocks of the 3-D IC integration technology are Through-Silicon Via (TSV) fabrication/implementation, thin wafer handling, low-temperature backside TSV revealing process, and electrical redistribution or connection of vertical circuitry or ICs. Of these elements, the scheme for wafer thinning and backside passivation is a crucial technology element of 3D integration. In this paper, novel backside via revealing and passivation for 3D IC application is proposed with newly developed process integration. Si/Cu CMP process is applied to overcome the practical limitations on the uniformity of the backside thinning originated from the blind thinning process. As such, the height variations associated with via etch non-uniformity and glue, carrier and grinding TTV's (Total Thickness Variation) are flattened out. In order to protrude the TSV from the backside, we demonstrated new spin wet etchback process with well-controlled repeatability, reduced process defect and copper contamination. For the low-k thick dielectric layer application (without photo-litho), Insulation layer on the back side is deposited over the protruded portion of the TSV structure. The deposited insulation layer is removed and TSV area is again exposed. The process for removing this insulation layer is the plasma etching or CMP polish. |
| Starting Page | 1395 |
| Ending Page | 1399 |
| File Size | 2797629 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781612844978 |
| ISSN | 05695503 |
| e-ISBN | 9781612844985 |
| e-ISBN | 9781612844961 |
| DOI | 10.1109/ECTC.2011.5898694 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-05-31 |
| Publisher Place | Florida, USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Through-silicon vias Copper Silicon Dielectrics Passivation Insulation Three dimensional displays |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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