NDLI: Reliability Assessment of Through-Silicon Vias in Multi-Die Stack Packages

Content Provider	IEEE Xplore Digital Library
Author	Xi Liu Qiao Chen Sundaram, V. Simmons-Matthews, M. Wachtler, K.P. Tummala, R.R. Sitaraman, S.K.
Copyright Year	2001
Abstract	A thermo-mechanical reliability study of through-silicon vias (TSVs) is presented in this paper. TSVs are used to interconnect stacked dies to achieve 3-D packages. As the core of the TSV contains high coefficient of thermal expansion (CTE) copper surrounded by low-CTE SiO₂ and Si materials, the thermo-mechanical reliability of TSVs is a concern. When dies with such TSVs are stacked and packaged, the presence of additional structures and associated materials could introduce different thermo-mechanical concerns compared with free-standing wafers. This paper presents 3-D finite-element models for studying the thermo-mechanical stresses in TSVs in free-standing wafers and in stacked dies, which are packaged. Warpage measurements have been used to validate the finite-element modeling approach. The results from the finite-element models show that the TSV stresses in a packaging configuration are typically lower than the TSV stresses in a free-standing wafer configuration. In addition, it is seen that the microbumps connecting adjacent dies experience high magnitude of inelastic strain, indicating that such locations are of reliability concern.
Sponsorship	IEEE Electron Devices Society IEEE Reliability Society
Starting Page	263
Ending Page	271
Page Count	9
File Size	1266055
File Format	PDF
ISSN	15304388
Volume Number	12
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Through-silicon vias Strain Copper Stress Three dimensional displays Thermomechanical processes Substrates 3-D packaging Finite-element (FE) modeling stacked dies thermo-mechanical stress analysis through-silicon via (TSV)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Safety, Risk, Reliability and Quality Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Structure Design Optimization and Reliability Analysis on a Pyramidal-Shape Three-Die-Stacked Package With Through-Silicon Via

Thermomechanical Characteristics of Copper Through-Silicon via Structures

Through-Strata-Via (TSV) Parasitics and Wideband Modeling for Three-Dimensional Integration/Packaging

Thermo-Mechanical Design Rules for the Fabrication of TSV Interposers

Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration

A Study on the Thermomechanical Reliability Risks of Through-Silicon-Vias in Sensor Applications

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Investigations of Thermomechanical Stress Induced by TSV-Middle (Through-Silicon via) in 3-D ICs by Means of CMOS Sensors and Finite-Element Method

Reliability Assessment of Through-Silicon Vias in Multi-Die Stack Packages

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