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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Too, S.S. Khan, M. Lim, K. Loo, M. Lau, W.C. Nayan, A. Ng, S.F. Peh, B.L. Goh, E. |
| Copyright Year | 2011 |
| Description | Author affiliation: Advanced Micro Devices, Inc., 1 AMD Place, PO Box 3453, MS103, Sunnyvale CA 94088-3453 USA (Too, S.S.; Khan, M.; Lim, K.; Loo, M.) || Advanced Micro Devices Singapore Pte. Ltd. Singapore (Goh, E.) || Advanced Micro Devices Export Sdn Bhd, Bayan Lepas FTZ, Phase 3, Penang, Malaysia (Lau, W.C.; Nayan, A.; Ng, S.F.; Peh, B.L.) |
| Abstract | In response to ever-increasing demand for computing power, a high-end server microprocessor with two silicon die in a multi-chip module (MCM) package was planned. For the MCM microprocessor to work optimally, the two large silicon die (each with more than 10,000 C4 bumps) need to communicate efficiently with each other. This requires many copper routing traces in the organic substrate. To accommodate the high quantity of routing traces, fine-pitch PTH package construction is necessary. Thin-core substrate was selected to enable fine-pitch PTH in the substrate with the added benefit of electrical signal integrity. A large (42.5 mm × 60.0 mm) organic MCM package with thin-core (400 microns thick) construction was therefore selected. The large thin-core bare substrate has very high and non-uniform warpage, up to 400 microns at room temperature. Each MCM substrate warps in different directions. This has created major flip-chip assembly challenges. Among the challenges are non-contact and partial joint formation, especially at die edges or die corners. Comprehensive shadow moiré and high-temperature warpage analysis were carried out to characterize the bare substrate warpage throughout the reflow temperature range. Shadow moiré analysis shows the substrate warpage changes significantly with temperature. To overcome this problem, an innovative assembly process and fixture were developed to ensure substrate flatness. To meet the lead-free packaging roadmap, it was decided to launch this MCM server microprocessor with lead-free C4 solder. Lead-free C4 solder has a separate set of assembly challenges. Lead-free solder is harder and less ductile, so creeps less after C4 joint formation. This results in higher die and package warpage. High die warpage indicates higher stress in the die, which becomes more prone to die crack. Higher warpage also increases the difficulty of the subsequent process of attaching a lid with indium thermal interface material (TIM). A comprehensive study of warpage between SnPb and lead-free solder was conducted. All assembly manufacturability problems were finally resolved with innovative assembly processes, tooling, and substrate improvement. A high-performance MCM server microprocessor was successfully launched, after significant development effort, with several MCM test vehicles. This paper details the assembly challenges, and the systematic methodology used to overcome them. |
| Starting Page | 517 |
| Ending Page | 522 |
| File Size | 2607813 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781612844978 |
| ISSN | 05695503 |
| e-ISBN | 9781612844985 |
| e-ISBN | 9781612844961 |
| DOI | 10.1109/ECTC.2011.5898560 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-05-31 |
| Publisher Place | Florida, USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Substrates Assembly Lead Silicon Routing Joints |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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