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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Oikawa, R. |
| Copyright Year | 2011 |
| Description | Author affiliation: Renesas Electronics Corporation, 1753, Shimonumabe, Nakahara-Ku, Kawasaki, Kanagawa, 211-8668, Japan (Oikawa, R.) |
| Abstract | A mitigation of the multi-gigabit SSO noise interference from the I/O buffer to the pre-driver in a DDR4 interface is demonstrated by utilizing a parasitic low-pass noise filter inside the low-cost wire-bonding packages. By optimizing the mutual inductance between I/O driver's and pre-driver's power supplies, the on-die decoupling capacitance of the 32bit DDR4 interface operating at 2133Mbps has been successfully reduced by 66–75% with keeping signal quality. A scaling issue in the SSO noise interference analysis is also addressed in this study by employing a domain partitioning technique based on whether individual power supply is closed or open system on the electrical charge. The design study has demonstrated the advantage of the low-cost wire-bonding packages when used for multi-gigabit single-ended interface, which also suggests the design direction and possibility of the over-2Gbps DDR interface with the wire-bonding packages. |
| Starting Page | 1864 |
| Ending Page | 1869 |
| File Size | 1487912 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781612844978 |
| ISSN | 05695503 |
| e-ISBN | 9781612844985 |
| e-ISBN | 9781612844961 |
| DOI | 10.1109/ECTC.2011.5898769 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-05-31 |
| Publisher Place | Florida, USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Noise Power supplies Driver circuits Integrated circuit modeling Capacitance Impedance Logic circuits |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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