NDLI: Digital architecture of the new ATLAS pixel chip FE-I4

Content Provider	IEEE Xplore Digital Library
Author	Hemperek, T. Arutinov, D. Barbero, M. Beccherle, R. Darbo, G. Dube, S. Elledge, D. Fougeron, D. Garcia-Sciveres, M. Gnani, D. Gromov, V. Karagounis, M. Kluit, R. Kruth, A. Mekkaoui, A. Menouni, M. Schipper, J.D. Wermes, N.
Copyright Year	2009
Description	Author affiliation: Lawrence Berkeley National Laboratory, 1 cyclotron road, Berkeley, CA 94720, United Sates of America (Dube, S.; Elledge, D.; Garcia-Sciveres, M.; Gnani, D.; Mekkaoui, A.) \|\| CPPM Aix-Marseille Université, CNRS/IN2P3, Marseille France (Fougeron, D.; Menouni, M.) \|\| National Institute for Subatomic Physics, Science Park 105, 1098 XG Amsterdam, The Netherlands (Gromov, V.; Kluit, R.; Schipper, J.D.) \|\| INFN Genova, via Dodecaseno 33, IT-16146 Genova, Italy (Beccherle, R.; Darbo, G.) \|\| University of Bonn, Physics Department, Nussallee 12, D-53115 Bonn, Germany (Hemperek, T.; Arutinov, D.; Barbero, M.; Karagounis, M.; Kruth, A.; Wermes, N.)
Abstract	With the high hit rate foreseen for the innermost layers at an upgraded LHC, the current ATLAS Front-End pixel chip FE-I3 [1] would start being inefficient. The main source of inefficiency comes from the copying mechanism of the pixel hits from the pixel array to the end of column buffers. A new ATLAS pixel chip FE-I4 is being developed in a 130 nm technology for use both in the framework of the Insertable B-Layer (IBL) project and for the outer layers of Super-LHC. FE-I4 is made of 80×336 pixels and features a reduced pixel size of 50×250 μm2. In the current design, a new digital architecture is introduced in which hit memories are distributed across the entire pixel array and the pixels organized in regions. In this paper, the digital architecture of FE-I4 is presented as well as the complete data flow.
Starting Page	791
Ending Page	796
File Size	876281
Page Count	6
File Format	PDF
ISBN	9781424439614
ISSN	10957863
DOI	10.1109/NSSMIC.2009.5402304
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Large Hadron Collider Circuits Clocks Physics Nuclear and plasma sciences Memory Digital recording Fires Frequency Delay
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Digital Architecture of the New ATLAS Pixel Chip FE-I4

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