NDLI: A vertically integrated 3D CMOS MAPS with in-pixel digital memory and delayed readout

Content Provider	IEEE Xplore Digital Library
Author	Degerli, Y. Bertolone, G. Dulinski, W. Guilloux, F. Morel, F. Orsini, F. Wei, X. Winter, M.
Copyright Year	2009
Description	Author affiliation: CEA Saclay, IRFU/SEDI, 91191 Gif-sur-Yvette, France (Degerli, Y.; Guilloux, F.; Orsini, F.) \|\| IPHC, IN2P3/ULP, 23 rue du Loess, 67037 Strasbourg, France (Bertolone, G.; Dulinski, W.; Morel, F.; Wei, X.; Winter, M.)
Abstract	In this paper, a novel 3D integrated rolling shutter mode binary pixel architecture, RSBPix (Rolling Shutter Binary PIXel), for charged particle tracking is presented. The analog part of the pixel consists of an n-well/p-substrate diode, a first amplification stage, a first double sampling circuitry, and a discriminator. The discriminator is made up of an offset-compensated multi-stage preamplifier and a latch. This approach allows to overcome process related mismatches of transistors and is compatible with low-voltage operation. During the integration phase, the pixels are selected row-by-row for amplification, discrimination and memorization of hits. This cycle is repeated sequentially during the arrival of bunches. Then, the memorized binary data of pixels corresponding to particle hits are readout slowly. A first prototype using RSBPix architecture has been designed in the Tezzaron & Chartered 3D-2Tier 130 nm CMOS process. The analog tier includes an array of 40×240 pixels divided in 9 sub-arrays with different diode sizes and transistor types. The pixel pitch is 20 μm, the chip size ~1.2 mm × 5.5 mm, and the power dissipation of the pixel ~120 μW. The pixel is readout in 80 ns. For test purpose, analog signals of 8 columns -out of 40 - can be observed directly, since their outputs are available without discriminators. Analog output buffers are also included on this tier. The digital tier includes a sequencer and output multiplexers for binary outputs. At the end of the readout chain, the digitized data are multiplexed on 8 outputs. Due to the limited design time, only a 1-bit memory was used for the pixel on this chip. All I/O pads are on the digital tier, and the analog tier is supplied by this one.
Starting Page	1631
Ending Page	1635
File Size	2218498
Page Count	5
File Format	PDF
ISBN	9781424439614
ISSN	10957863
DOI	10.1109/NSSMIC.2009.5402258
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Diodes Particle tracking Sampling methods Circuits Preamplifiers Latches Prototypes CMOS process Power dissipation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in