NDLI: The L1 track trigger and high data rate acquisition system for the SLIM5 beam test

Content Provider	IEEE Xplore Digital Library
Author	Villa, M.
Copyright Year	2009
Description	Author affiliation: Bologna University and INFN, I-40126 Bologna, Italy (Villa, M.)
Abstract	In September 2008 the Slim5 collaboration submitted a low material budget silicon demonstrator to test with 12 GeV/c protons, at the PS-T9 test-beam at CERN. The beam test setup was composed of two different detectors (DUTs) placed inside a reference microstrip silicon tracker telescope. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130 Nm CMOS Technology, providing digital sparsified readout. The other one was a high resistivity double sided silicon detector, with short strips at 45 angle to the detector's edge, read out by FSSR2 chips. In total, the set-up contained 38 chips for 12k individual electronic channels. The data acquisition of the experiment was done by means of two high bandwidth, fully programmable 9U VME board (EDRO) that have been designed to stand a 12 Gbit/s input rate, 1.2 Gbit/s output rate and have the possibility to perform different types of trigger strategies on data. The most important one was the on-line track identification performed with the help of an Associative Memory board, which demonstrated the capability of the setup to trigger on identified tracks with a minimal latency (< 1μs). In the contribution, the beam test setup, the data acquisition and trigger systems are presented. The main remarkable trigger and data acquisition performances (2.5 MHz event evaluation rate, 40 kHz data acquisition rate, event selection on identified tracks) that lead to a successful data taking are discussed.
Starting Page	772
Ending Page	776
File Size	438117
Page Count	5
File Format	PDF
ISBN	9781424439614
ISSN	10957863
DOI	10.1109/NSSMIC.2009.5402251
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System testing Data acquisition Silicon Materials testing CMOS technology Collaboration Protons Microstrip Telescopes Transmission line matrix methods Tracking Data Acquisition DAQ FPGA VME Trigger
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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