NDLI: The electronics in the detector head of the AGIPD detector — A 1MPixel, 5MHz camera for the European XFEL

Content Provider	IEEE Xplore Digital Library
Author	Gottlicher, P.
Copyright Year	2009
Description	Author affiliation: Deutsches Elektronen-Synchrotron, Hamburg, Germany (Gottlicher, P.)
Abstract	The European free electron laser (XFEL) will provide trains of 12.4 keV X-ray photons. With a repetition frequency of 10Hz 0.6ms long trains with 3000 bunches will be generated with a bunch to bunch separation of 200 ns. For experiments at XFEL the AGIPD consortium is developing a 2-dimensional 1Mega pixel detector to record individual pictures for bunches separated by 200 ns. As a first step ≈200 pictures per train will be stored as analogue values in capacitors inside ASIC's. To minimize charge leakage a fast digitization system will be developed as a board level electronic system housed in the detector head. In the baseline design it will handle up to 400 pictures/train. 1024 ADC's each with 50MS/s and 14 bit will be mounted in 16 modules and generate a data rate of 16×51 Gbit/s into 16 FPGA's, one per module. After correction and pre-sorting the data of each module will be sent on a standard IT 10Gb/s fibre link to the backend system. IP protocols are targeted for use in data transfer and VHDL code for the VIRTEX-5 FPGA has been implemented. Performance tests show that 99% payload link occupancy can be achieved, well above the required 55%. Control of the detector head and it's synchronization will be performed using dedicated differential signal lines passing clock and event signals between the accelerator timing system receiver and control master and the detector head FPGA's. Slow control and train synchronous information exchange (100ms) will be implemented using reliable TCP/IP Ethernet with the messages passed between detector head microcontrollers and the control master. The basic building blocks required have been investigated with evaluation boards and in-house developments.
Starting Page	1811
Ending Page	1816
File Size	2361961
Page Count	6
File Format	PDF
ISBN	9781424439614
ISSN	10957863
DOI	10.1109/NSSMIC.2009.5402195
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Detectors Cameras Field programmable gate arrays X-ray lasers Control systems Event detection Free electron lasers Frequency Capacitors Leak detection Camera X-ray XFEL AGIPD Hybrid pixel detector
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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