NDLI: IDeF-X SX0: A low power CMOS ASIC for the readout of Cd(Zn)Te detectors

Content Provider	IEEE Xplore Digital Library
Author	Gevin, O. Lugiez, F. Delagnes, E. Limousin, O. Meuris, A.
Copyright Year	2009
Description	Author affiliation: CEA Saclay DSM/IRFU/Service d'Electronique, de Détecteurs et d'Informatique, bât. 141, 91191 Gif-sur-Yvette, France (Gevin, O.; Lugiez, F.; Delagnes, E.) \|\| CEA Saclay DSM/IRFU/Service d'Astrophysique, bât. 709 L'Orme des Merisiers, 91191 Gif-sur-Yvette, France (Limousin, O.; Meuris, A.)
Abstract	The last member of the IDeF-X ASIC family is presented: IDeF-X SX0 a 32-channel front end ASIC designed for the readout of Cadmium Telluride (CdTe) and Cadmium Zinc Telluride (CdZnTe) Detectors. It has been designed in the standard AMS CMOS 0.35 μm process technology. The ASIC has been optimized to reduce the power consumption which is now 600 μW per channel; it is five times lower than the power consumption of the previous IDeF-X ECLAIRs chip [1]. Moreover, the dynamic range of the ASIC can now be extended to more than 1 MeV thanks to the in-channel variable gain stage. When no detector is connected to the chip, the lowest equivalent noise charge (ENC), achieved at a 9 μs peak time, is 72 electrons rms. IDeF-X SX0 has been evaluated by performing spectroscopy measurements at room temperature with a thin CdTe Schottky detector. The energy resolution was found to be 1.6 keV fwhm at 60 keV with an $^{241}Am$ source. The ASIC has been designed for space applications and it will be used for the readout of 16 × 16 pixels CdTe or CdZnTe pixellated detectors to build a new low power Caliste micro Gamma camera [2].
Starting Page	318
Ending Page	321
File Size	414005
Page Count	4
File Format	PDF
ISBN	9781424439614
ISSN	10957863
DOI	10.1109/NSSMIC.2009.5401726
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Detectors Cadmium compounds Energy consumption Temperature measurement Zinc compounds CMOS process CMOS technology Dynamic range Gain Hard X-ray spectroscopy CMOS ASIC Noise CdTe CdZnTe
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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IDeF-X ECLAIRs: An ultra low noise CMOS ASIC for the readout of Cd(Zn)Te detectors

IDeF-X ECLAIRs: A CMOS ASIC for the Readout of CdTe and CdZnTe Detectors for High Resolution Spectroscopy

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IDeF-X V1.0: performances of a new CMOS multi channel analogue readout ASIC for Cd(Zn)Te detectors

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A low noise readout ASIC for CdTe/CdZnTe detectors

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IDeF-X SX0: A low power CMOS ASIC for the readout of Cd(Zn)Te detectors

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