NDLI: Characterization of CMOS position sensitive solid-state photomultipliers

Content Provider	IEEE Xplore Digital Library
Author	McClish, M. Dokhale, P. Christian, J. Stapels, C. Robertson, R. Shah, K.S.
Copyright Year	2009
Description	Author affiliation: Radiation Monitoring Devices, Inc., Watertown, MA 02472 USA (McClish, M.; Dokhale, P.; Christian, J.; Stapels, C.; Robertson, R.; Shah, K.S.)
Abstract	We have designed position sensitive solid-state photomultipliers (PS-SSPM) using a complementary metal-oxide-semiconductor (CMOS) process. Four variations of the PS-SSPM design were fabricated, however, only three were characterized for their energy and coincidence timing resolution, spatial resolution, and scintillator array imaging. Each PS-SSPM is 1.5 × 1.5 $mm^{2},$ however, each device has different micro-pixel geometries and different micro-pixel electrical readout for event position sensing. When coupled to 1 × 1 × 20 $mm^{3}$ LYSO, the energy resolution at 511 keV was measured as a function of bias. The same LYSO scintillator was used to measure the coincidence timing resolution. Results varied from 2.1 ns to 1.0 ns (FWHM) at 511 keV. Spatial resolution studies were conducted using a focused (~ 15 μm beam spot diameter) pulsed 635 nm diode laser. For each PS-SSPM, the X and Y FWHM spatial resolution was measured between 70 and 75 μm (FWHM). Lastly, a scintillator array studies were conducted for each PS-SSPM using a CsI:Tl and LYSO array having 300 × 300 $μm^{2}$ and 500 × 500 $μm^{2}$ pixels respectively.
Starting Page	1431
Ending Page	1436
File Size	508939
Page Count	6
File Format	PDF
ISBN	9781424439614
ISSN	10957863
DOI	10.1109/NSSMIC.2009.5402319
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Solid state circuits Photomultipliers Spatial resolution Energy resolution CMOS image sensors Timing CMOS process Image resolution Geometry Energy measurement solid-state photomultiplier Avalanche photodiodes Geiger-mode position sensitive
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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