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FE-I4 ATLAS Pixel Chip Design
| Content Provider | Semantic Scholar |
|---|---|
| Author | Barbero, Marlon Beccherle, Roberto Schipper, J. D. Fougeron, Denis Gnani, Dario Hemperek, Tomasz Garcia-Sciveres, Maurice Elledge, David Wermes, Norbert Mekkaoui, A. Karagounis, Michael Arutinov, David Menouni, Mohsine Kluit, Ruud Darbo, Giovanni Kruth, Andre Gromov, Vladimir Dube, Sourabh |
| Copyright Year | 2009 |
| Abstract | FE-I4 is the new ATLAS pixel chip developed for use in upgraded luminosity environments, in the framework of the Insertable B-Layer (IBL) project but also for the outer pixel layers of Super-LHC. It is designed in a 130 nm CMOS process and is based on an array of 80 by 336 pixels, each 50×250 μm for an overall size of about 19×20 mm. Each pixel consists of analog and synthesized digital sections. The analog pixel section is designed for low power consumption and compatibility to several sensor candidates. The digital architecture is based on a 4 pixel unit called region, which allows for a power-efficient, low recording inefficiency design, and provides a solution to record hits timewalk-free. A mixture of techniques is used for yield enhancement. The chip periphery contains a control block, a command decoder and global memory, powering blocks, a data reformatting unit, an asynchronous storage FIFO, an 8b10b coder and a clock multiplier unit, which allows data transmission up to 160 Mb/s for the IBL. |
| Starting Page | 027 |
| Ending Page | 027 |
| Page Count | 1 |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://pos.sissa.it/095/027/pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
