NDLI: Thin, fully depleted monolithic active pixel sensor based on 3D integration of heterogeneous CMOS layers

Content Provider	IEEE Xplore Digital Library
Author	Dulinski, W. Bertolone, G. de Masi, R. Degerli, Y. Dorokhov, A. Morel, F. Orsini, F. Ratti, L. Santos, C. Re, V. Wei, X. Winter, M.
Copyright Year	2009
Description	Author affiliation: University of Pavia and INFN Sezione di Pavia, Italy (Ratti, L.) \|\| CEA Saclay, IRFU/SEDI, 91191 Gif-sur-Yvette, France (Degerli, Y.; Orsini, F.) \|\| University of Bergamo and INFN Sezione di Pavia, Italy (Re, V.) \|\| IPHC, IN2P3/ULP, 23 rue du Loess, 67037 Strasbourg, France (Dulinski, W.; Bertolone, G.; de Masi, R.; Dorokhov, A.; Morel, F.; Santos, C.; Wei, X.; Winter, M.)
Abstract	On the way towards fast, radiation tolerant and ultra thin CMOS radiation sensors, we propose new generation of devices based on commercial availability of vertical integration of several CMOS wafers (3D Electronics). In this process, each wafer may be thinned down to about 10 microns end equipped with through-silicon vias (TSV) allowing for electrical interconnection between wafers at a very small pitch (few microns) and with a minimum material budget. The proposed prototype device is a 245×245 pixel array with a pitch of 20 μm, providing active area of 5×5 mm2. In the first silicon layer charge sensing diode and first stage buffer amplifier (source follower) are integrated, using CMOS process on high resistivity epitaxial wafers. Outputs of buffer voltage amplifiers are vertically coupled (through a poly-poly capacitor) to the following stage of processing electronics (charge integration, time continuous shaping and signal discrimination), placed in the second silicon layer (0.13 micron CMOS). The third silicon layer (also 0.13 micron CMOS) is used for implementation of digital (binary) readout with a fast, data driven, self-triggering data flow. After description of the proposed 3D device, an update of results from ongoing tests with the first CMOS MAPS prototype fabricated using high-resistivity epitaxial substrate is provided.
Starting Page	1165
Ending Page	1168
File Size	510843
Page Count	4
File Format	PDF
ISBN	9781424439614
ISSN	10957863
DOI	10.1109/NSSMIC.2009.5402398
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon Through-silicon vias Prototypes CMOS process Diodes Conductivity Voltage Capacitors Signal processing Testing
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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