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Content Provider | IEEE Xplore Digital Library |
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Author | Yong Liu Qiuxiao Qian Ring, M. Jihwan Kim Kinzer, D. |
Copyright Year | 2012 |
Description | Author affiliation: Fairchild Semiconductor Corp, 82 Running Hill Road, Mail Stop 35-2E, South Portland, ME 04106 (Yong Liu; Qiuxiao Qian; Ring, M.; Jihwan Kim; Kinzer, D.) |
Abstract | Comprehensive finite element analysis (FEA) modeling is carried out to improve the performance of critical designs of wafer level chip scale package (WLCSP). First, a design with one layer redistribution layout (RDL) copper with etched pocket in the non-covered UBM area and one layer polyimide structure (1Cu1Pi design) is investigated. Different polyimide layouts, copper thicknesses, pocket parameters and non-covered UBM diameters are studied through finite element modeling. Then, a stacked metal design with the sputtered copper UBM stacked on the RDL copper layer, with one polyimide layer between them (2Cu1Pi) for the WLCSP is examined. Parameter study of different UBM diameters with the same solder volume and different UBM diameters with the same solder joint height is conducted by the simulation. Finally the correlation and comparison of the failure mechanism between the modeling and the test are presented and discussed. |
Starting Page | 1174 |
Ending Page | 1182 |
File Size | 2363347 |
Page Count | 9 |
File Format | |
ISBN | 9781467319669 |
ISSN | 05695503 |
e-ISBN | 9781467319652 |
e-ISBN | 9781467319645 |
DOI | 10.1109/ECTC.2012.6248985 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2012-05-29 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Polyimides Layout Finite element methods Copper Stress Soldering Semiconductor device modeling |
Content Type | Text |
Resource Type | Article |
Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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