NDLI: 3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism

Content Provider	IEEE Xplore Digital Library
Author	Chang-Chun Lee Hsing-Chih Liu Kuo-Ning Chiang
Copyright Year	1999
Abstract	With the present trend of multifunction and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLPs) and chip scale packages (CSPs) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP) with a stress buffer layer and bubble-like plate (Fig. 1) are proposed in this research to improve the solder joint fatigue life. The thermal stress caused by the coefficient of thermal expansion mismatch can be significantly reduced, and the reliability of the WLP could be substantially enhanced by this new design. In order to realize the relationship of the solder joint fatigue life, stress buffer layer and bubble-like plate, a finite element parametric analysis applying software ANSYS is utilized. In additions, the methodology based on the finite element method (FEM) used in the study has been verified by the relative experiments in our previous researches. The design parameters include the thickness of the stress buffer layer, thickness, bending angle and standoff height of the different types of bubble-like plate. The results of the FEM analysis reveal that the stress buffer layer and bubble-like plate can relax the thermal stresses of solder joints and enhance the package reliability. Besides, the peeling stress between stress buffer layer and two different types of bubble-like plates is discussed, and the stress state of the leadframe is also analyzed in this research. Furthermore, the findings of this research can be used as the guideline for advanced WLCSP design
Sponsorship	IEEE Components, Packaging, and Manufacturing Technology Society
Starting Page	110
Ending Page	118
Page Count	9
File Size	1319375
File Format	PDF
ISSN	15213331
Volume Number	30
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-03-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer scale integration Thermal stresses Electronic packaging thermal management Buffer layers Chip scale packaging Electronics packaging Soldering Fatigue Thermal expansion Finite element methods wafer level packages (WLP) Bubble-like stress buffer layer chip scale packages (CSP) finite element method (FEM) reliability simulation
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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