NDLI: Camera head of the DSSC X-ray imager

Content Provider	IEEE Xplore Digital Library
Author	Hansen, K. Klar, H. Muntefering, D.
Copyright Year	2011
Description	Author affiliation: Max-Planck-Institut für extraterristrische Physik (MPE), 85741 Garching, Germany (Muntefering, D.) \|\| Deutsches Elektronen-Synchrotron (DESY), 22607 Hamburg, Germany (Hansen, K.; Klar, H.)
Abstract	A description of the camera-head electronics of the DSSC mega-pixel X-ray imager is given. The integration of 32 sensor chips, 256 ASICs, 112 PCBs, and 16 flex cables in the space of 241mm × 251mm × 224mm underlines its compactness. Prototypes of subassemblies behind the readout-ASIC layer are designed and fabricated. Measurement results of the main functionalities clock distribution, power cycling, and clear-pulse generation are presented. A rms-timing jitter of 2.5 ps is achieved for the distribution of an 800-MHz ±290-mV clock signal. A settling time of 10 µs and a ripple in the millivolt range are achieved for 10-Hz cycling of the 1.2-V ASIC-power nets at a load current of 2.9 A. The feasibility of 600-µs long trains containing 60-ns FWHM pulses with 10-ns rise and fall times at a repetition rate of 4.5MHz is demonstrated. Low and high levels are adjustable between 2V and 22.5V for a 2.5-Ω∥3.6-nF load.
Starting Page	1713
Ending Page	1717
File Size	2140250
Page Count	5
File Format	PDF
ISBN	9781467301183
ISSN	10823654
e-ISBN	9781467301206
DOI	10.1109/NSSMIC.2011.6154666
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-23
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Photonics Europe Force Clocks Timing Field programmable gate arrays Decision support systems XFEL X-ray camera pixel detector DEPFET power cycling pulse generation clock distribution DSSC
Content Type	Text
Resource Type	Article

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