NDLI: Alignment and overlay characterization for 3D integration and advanced packaging

Content Provider	IEEE Xplore Digital Library
Author	v. Zeijl, H.W. Sarro, P.M.
Copyright Year	2009
Description	Author affiliation: Laboratory of Electronic Materials Devices and Components (ECTM), DIMES, DELFT University of Technology (v. Zeijl, H.W.; Sarro, P.M.)
Abstract	The alignment and overlay performance of an ASML PAS5000 waferstepper is reviewed in relation to 3D integration and wafer level packaging (WLP) processes. The alignment system can be used to measure substrate distortions in wafer bonding and waferthinning processes and it can align with high accuracy through thick films. Moreover, it is demonstrated that in through silicon vias (TSV) processing the front- to backwafer overlay accuracy is limited by the etch process, not by the alignment system. An accurate fully functional alignment system can therefore be used to characterize and improve the overlay in 3D integration and WLP processes.
Starting Page	447
Ending Page	451
File Size	1258240
Page Count	5
File Format	PDF
ISBN	9781424450992
e-ISBN	9781424451005
DOI	10.1109/EPTC.2009.5416504
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-09
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Packaging Lithography CMOS technology Fabrication Optical distortion Optical films Wafer scale integration Production Electric variables measurement Distortion measurement
Content Type	Text
Resource Type	Article

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