NDLI: Through Silicon Vias Technology for CMOS Image Sensors Packaging: Presentation of Technology and Electrical Results

Content Provider	IEEE Xplore Digital Library
Author	Henry, D. Charbonnier, J. Chausse, P. Jacquet, F. Aventurier, B. Brunet-Manquat, C. Lapras, V. Anciant, R. Sillon, N. Dunne, B. Hotellier, N. Michailos, J.
Copyright Year	2008
Description	Author affiliation: ST Microelectron, Crolles, France (Hotellier, N.; Michailos, J.) \|\| ST Microelectron., Rousset, France (Dunne, B.) \|\| CEA-LETI, MINATEC, Grenoble, France (Henry, D.; Charbonnier, J.; Chausse, P.; Jacquet, F.; Aventurier, B.; Brunet-Manquat, C.; Lapras, V.; Anciant, R.; Sillon, N.)
Abstract	In this paper a low temperature 'via-last' technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. In the first part of this paper, the design of the TSV will be presented and a first approach of a design rule definition for TSV will be introduced. The alignment strategy will be also presented, and specific patterns to succeed front side to back side alignment will be described. In a second part the steps of the Through Silicon Vias (TSV) technology will be briefly presented: glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific steps like double side lithography, silicon deep etching, silicon side wall insulation, vias metallization and final bumping. Then, morphological characterizations of the via-last technology will be presented and discussed. Finally, electrical characterization including vias continuity, single via electrical resistance, insulation layer leakage current and breakdown voltage have been measured and will be discussed. A picture obtained with the TSV CMOS Image Sensor (TSV CIS) will be also shown.
Starting Page	35
Ending Page	44
File Size	10621376
Page Count	10
File Format	PDF
ISBN	9781424421176
DOI	10.1109/EPTC.2008.4763409
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-09
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology CMOS image sensors Packaging Through-silicon vias Silicon on insulator technology Wafer scale integration Temperature sensors Glass Wafer bonding Lithography Electrical measurements Through Silicon Vias (TSV) CMOS image sensors (CIS) Advanced packaging Wafer level technologies Design rules
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in