NDLI: Development and characterisation of high electrical performances TSV for 3D applications

Content Provider	IEEE Xplore Digital Library
Author	Henry, D. Cheramy, S. Charbonnier, J. Chausse, P. Neyret, M. Garnier, G. Brunet-Manquat, C. Verrun, S. Sillon, N. Bonnot, L. Farcy, A. Cadix, L. Rousseau, M. Saugier, E.
Copyright Year	2009
Description	Author affiliation: STMicroelectronics; 850 rue Jean MONNET; F-38926 CROLLES - France (Bonnot, L.; Farcy, A.; Cadix, L.; Rousseau, M.) \|\| STMicroelectronics; 12 rue Jules Horowittz; F-38000 Grenoble - France (Saugier, E.) \|\| CEA Léti - MINATEC; 17 rue des Martyrs; F-38054 GRENOBLE - France (Henry, D.; Cheramy, S.; Charbonnier, J.; Chausse, P.; Neyret, M.; Garnier, G.; Brunet-Manquat, C.; Verrun, S.; Sillon, N.)
Abstract	Today, a new trend in wafer level packaging is to add more than one die in the same package and, sometimes, to use the third dimension in order to : • Decrease the form factor of the final system • Improve the thermal and electrical performances of the device • Decrease the cost of the final product In order to stack the heterogeneous components in the third dimension, TSV (Through Silicon Vias) is a very promising technology compare to wire bonding. In this paper, the technological bricks specifically developed for 3D integration demonstrator will be presented. The integration flow was based on the 45 nm technology top chip stacked on a 130 nm technology active bottom wafer [1] [2]. This flow needed to develop specific wafer level packaging technologies such as: • Top chip & bottom chip interconnections • High aspect ratio TSV included into the bottom wafer • Backside interconnections for subsequent packaging step • Temporary bonding and debonding of bottom wafer [3] [4] • Top chip stacking on bottom wafer In the first part of the paper, the complete process flow will be presented. Then, a technical focus will be done on the specific steps developed for the improvement of the TSV's electrical performances. Finally, the electrical results achieved on a specific test vehicle, similar to the demonstrator will be discussed. The electrical results obtained on a technological test vehicle will be firtly presented. Those results include electrical continuity, pillars resistance, TSV resistance and capacitance and TSV insulation and current losses. Then, the electrical results obtained with the “high electrical performances” process on the functionnal demonstrator will be showed, including a specific focus on the TSV capacitance measurements.
Starting Page	528
Ending Page	535
File Size	1499775
Page Count	8
File Format	PDF
ISBN	9781424450992
e-ISBN	9781424451005
DOI	10.1109/EPTC.2009.5416490
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-09
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Through-silicon vias Wafer scale integration Packaging Wafer bonding Testing Vehicles Electric resistance Thermal factors Costs Silicon parasitic capacitance Trough Silicon Vias (TSV) Wafer level Packaging Stacking back side connections
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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