NDLI: Assembly and reliability of micro-bumped chips with Through-silicon Vias (TSV) interposer

Content Provider	IEEE Xplore Digital Library
Author	Yue Ying Ong Tai Chong Chai Daquan Yu Meei Leng Thew Eipa Myo Leong Ching Wai Ming Chinq Jong Rao, V.S. Su, N. Xiaowu Zhang Damaruganath, P.
Copyright Year	2009
Description	Author affiliation: Institute of Microelectronics, A¿STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore, Science Park II, Singapore 117685 (Yue Ying Ong; Tai Chong Chai; Daquan Yu; Meei Leng Thew; Eipa Myo; Leong Ching Wai; Ming Chinq Jong; Rao, V.S.; Su, N.; Xiaowu Zhang; Damaruganath, P.)
Abstract	This paper presents the assembly optimization and charcterierization of Through-Silicon Vias (TSV) interposer technology for two 8 × $10mm^{2}$ micro-bumped chips. The two micro-bumped chips represent different functional dies in a System-in-package (SiP). In the final test vehicle, one of the micro-bumped chips had 100μm bump pitch and 1,124 I/O; the other micro-bumped chip had 50μm bump pitch and 13,413 I/O. The TSV interposer size is 25 × 25 × $0.3mm^{3}$ with CuNiAu as UBM on the top side and SnAgCu bumps on the underside. The conventional substrate size is 45 × $45mm^{2}$ with 1-2-1 layer configuration, a ball-grid array (BGA) of 1mm pitch and a core thickness of 0.8mm. The final test vehicle was subjected to MSL3 and TC reliability assessment. The objective of this paper was to incorporate two 8 × $10mm^{2}$ micro-bumped chips into TSV interposer. The micro-bumped chips should have no underfill voiding issue and the whole package should be able to pass Moisture Sensitivity Level 3 (MSL3) and Thermal Cycling (TC) reliability assessment. To achieve this objective of incorporating micro-bumped chips into the TSV interposer, the challenges were small standoff height/ low bump pitch of the micro-bumped chip, underfill flowability and its reliability performance. To overcome these challenges, different types of capillary flow underfill, bump layout designs and bump types were evaluated and a quick reliability assessment was used to select the materials and test vehicle parameters for final assembly and reliability assessment.
Starting Page	452
Ending Page	458
File Size	2007471
Page Count	7
File Format	PDF
ISBN	9781424450992
e-ISBN	9781424451005
DOI	10.1109/EPTC.2009.5416505
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-09
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Through-silicon vias Assembly Silicon Vehicles Aluminum Testing Electronic packaging thermal management Materials reliability Metallization Passivation
Content Type	Text
Resource Type	Article

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