NDLI: Effect of TSV interposer on the thermal performance of FCBGA package

Content Provider	IEEE Xplore Digital Library
Author	Hoe, Y.Y.G. Tang Gong Yue Damaruganath, P. Chai Tai Chong Lau, J.H. Zhang Xiaowu Vaidyanathan, K.
Copyright Year	2009
Description	Author affiliation: Institute of Microelectronics, A¿STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore, Science Park II, Singapore 117685 (Hoe, Y.Y.G.) \|\| Hong Kong University of Science and Technology (Lau, J.H.) \|\| United Test and Assembly Center (UTAC) 5 Serangoon North Ave 5, Singapore 554916 (Tang Gong Yue)
Abstract	In this paper, the effect of TSV (Through Silicon Via) parameters on the equivalent thermal conductivity of TSV interposer and the effect of the TSV interposer on the thermal performance of the package have been elaborated. The modeling approach using in this paper includes compact modeling for the package and detailed modeling for the TSV interposer. The objective of compact modeling is to study the effect of TSV interposer on thermal performance of the package, while the objective of detailed modeling is to extract the equivalent thermal conductivity of TSV interposer which is used for compact modeling. The proposed package in this study includes a large die with fine pitch, a silicon interposer with TSV, a 1-2-1 buildup substrate and a PCB board. In addition, to evaluate the thermal performance of the proposed package, a similar package without the TSV interposer is also modeled in this study for comparison. The results of detailed modeling show that the equivalent thermal conductivity of TSV interposer can be increased by reducing the pitch and via ratio of TSV, as well as increasing the plating thickness of partial filled TSV and using highly conductive filler material. Furthermore, the results of compact modeling reveal that the proposed TSV interposer improves the thermal performance of the package. The thermal resistance of the package decreases when the interposer size and thickness increase, and the equivalent thermal conductivity of TSV interposer has negligible effect on thermal performance of the package.
Starting Page	778
Ending Page	786
File Size	591357
Page Count	9
File Format	PDF
ISBN	9781424450992
e-ISBN	9781424451005
DOI	10.1109/EPTC.2009.5416445
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-09
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Through-silicon vias Packaging Thermal conductivity Thermal resistance Silicon Microelectronics Wiring Thermal stresses Testing Assembly
Content Type	Text
Resource Type	Article

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