NDLI: 3D device integration

Content Provider	IEEE Xplore Digital Library
Author	Bauer, C.E. Neuhaus, H.J.
Copyright Year	2009
Description	Author affiliation: TechLead Corporation Portland, Oregon, USA (Bauer, C.E.; Neuhaus, H.J.)
Abstract	For more than a decade the industry has recognized the power of the third dimension in package and sub-system assembly for the implementation of highly integrated mobile electronic products. Numerous approaches have been reported and demonstrated including those base on package stacking (package-on-package, origami, and edge stacked modules) and those based on die stacking (wire bond, mixed technology, edge redistribution, and through-silicon-vias). Through-silicon-vias stand out from the others as the only true 3D device integration as opposed to 3D packaging method. Consequently, through silicon via technology presents unique opportunities and challenges. For example, through-silicon-vias promise unrivaled performance improvements due to short, low impedance interconnect and high silicon efficiency. On the other hand, no other 3D approach matches the disruption of the existing food chain. This paper reviews the challenges and opportunities of 3D device integration based on through-silicon-vias in terms of, processes, applications, challenges, and intellectual property landscape.
Starting Page	427
Ending Page	430
File Size	681153
Page Count	4
File Format	PDF
ISBN	9781424450992
e-ISBN	9781424451005
DOI	10.1109/EPTC.2009.5416508
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-09
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electronics packaging Stacking Silicon Electronics industry Assembly Industrial electronics Wire Bonding Food technology Impedance
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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