NDLI: Cost comparison for flip chip, gold wire bond, and copper wire bond packaging

Content Provider	IEEE Xplore Digital Library
Author	Palesko, C.A. Vardaman, E.J.
Copyright Year	2010
Description	Author affiliation: SavanSys Solutions, LLC 10409 Peonia Ct., Austin TX 78733 (Palesko, C.A.) \|\| TechSearch International, Inc. 4801 Spicewood Springs Road Suite 150, Austin TX 78759 (Vardaman, E.J.)
Abstract	When the cost of gold was $500 per ounce, the lowest cost packaging choice was clear-it was always gold wire bonding. However, with the cost of gold at more than $1,000 per ounce and significant cost decreases in flip chip package fabrication and assembly, the lowest cost packaging choice is no longer obvious. Gold wire bonding is one of the oldest and most mature process, and offers high yields and low processing $costs^{1}.$ Copper wire bonding is an alternative to save material cost, but is less mature and requires equipment $modifications^{2}.$ Historically, flip chip packages have only been cost effective for area-constrained applications given the additional wafer bumping cost and the high substrate cost. However, wafer bumping costs have decreased significantly in the past few years and low-cost flip chip substrates are now available in the market. This poster presentation will compare the total packaging cost from wafer preparation through final package assembly. The analysis will be done using a comprehensive activity based cost model for each of the three package technologies. All wafer preparation activities (bumping for flip chip, wafer mounting, backgrind, dicing, etc.), substrate fabrication activities (inner layer processing, build-up layer processing, drilling, surface finish, testing, singulation, etc.), and assembly activities (die bonding, wire bonding, underfill, mold compound, lid attach, solder ball attach, etc.) have been modeled and verified using multiple industry sources.
Starting Page	10
Ending Page	13
File Size	465563
Page Count	4
File Format	PDF
ISBN	9781424464104
ISSN	05695503
e-ISBN	9781424464128
e-ISBN	9781424464111
DOI	10.1109/ECTC.2010.5490877
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wire Costs Flip chip Gold Copper Assembly Fabrication Packaging machines Wafer bonding Semiconductor device modeling
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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