NDLI: Wafer level package using pre-applied anisotropic conductive films (ACFs) for flip-chip interconnections

Content Provider	IEEE Xplore Digital Library
Author	Ho-Young Son Chang-Kyu Chung Myung-Jin Yim Kyung-Wook Paik
Copyright Year	2006
Description	Author affiliation: Dept. of Mater. Sci. & Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon (Ho-Young Son; Chang-Kyu Chung; Myung-Jin Yim; Kyung-Wook Paik)
Abstract	Recently, wafer level package (WLP) has become one of the promising packaging technologies due to its advantages such as fewer processing steps, lower cost, and enhanced device performance compared to single chip packages. Many developments on new WLP design, material and process have been accomplished according to the electrical, mechanical performance and reliability requirement of the devices to be packaged. For the lower cost, higher performance and environmentally green packaging process, anisotropic conductive films (ACFs) flip chip assembly has been widely used such as ultra-fine pitch flat panel display (FPD) and general semiconductor packaging applications. However, there has been no previous attempt using on WLP. In this study, wafer level packages using pre-applied ACFs on a wafer for flip-chip interconnections have been investigated, and the effect of process parameters on the ACF wafer level package performance were investigated. After ACF lamination on an Au stud bumped wafer, and subsequent singulation, and singulated chips were flip-chip assembled on an organic substrate using a thermo-compression bonding method. Au stud bumps were well assembled on Ni/Au pads of organic substrates. And ACF joints between Au stud bumps and substrate pads showed stable bump contact resistance of 8~9mOmega per a bump. As a summary, new wafer level package method using pre-applied anisotropic conductive films was successively demonstrated for flip chip interconnections. As a result, the newly developed WLP using pre-applied ACFs can be widely used for many non-solder flip chip assembly applications
File Size	959071
File Format	PDF
ISBN	1424401526
ISSN	05695503
DOI	10.1109/ECTC.2006.1645705
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer scale integration Anisotropic conductive films Semiconductor device packaging Assembly Gold Flip chip Substrates Costs Process design Conducting materials
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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