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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Joshi, M. Pendse, R. Pandey, V. Lee, T.K. Yoon, I.S. Yun, J.S. Kim, Y.C. Lee, H.R. |
| Copyright Year | 2010 |
| Description | Author affiliation: STATS ChipPAC Inc (Joshi, M.; Pendse, R.; Pandey, V.; Lee, T.K.; Yoon, I.S.; Yun, J.S.; Kim, Y.C.; Lee, H.R.) |
| Abstract | Increased functionality requirements coupled with progressively reducing package size have necessitated the integration of flip chip packages into various baseband and application processor products in mobile platforms. Such products use flip chip technology using traditional capillary underfill (CUF) process on a strip based package which is subsequently over molded to finish the end-product assembly. The growing pricing pressures and competitive landscape in mobile-packaging has made it imperative for assembly subcontractors to drive the flip chip assembly cost down. To achieve this without compromising product reliability requires a fundamental shift in the way these packages are assembled. Molded underfill (MUF) approach offers such unique solution with promising advantages over CUF; such as lower material cost, higher through put and excellent reliability to meet the overall product needs of today's evolving mobile market; and is discussed in this paper. Capillary Underfill (CUF) has been the cornerstone of today's flip chip technology in both flip chip BGA and flip chip CSP format. Several advancements in CUF materials and dispense technologies made over years has made CUF the underfill technology of choice for various flip chip applications. However as the need for reducing package assembly cost has grown simultaneously; CUF material and underfill process comes under scrutiny due to higher material cost and slow through put process in the flip chip assembly flow. MUF was explored and found to be a viable lower cost alternative for mobile products by virtue of lower material cost and faster throughput due to batch process operation in strip format. The cost benefit is further complemented by the capability of MUF to enable finer spacing between die-to-die and die-to-passives; as well as smaller keep-out zones to enable reduced die-to-package edge clearance or effectively shrink the overall package size than that with CUF. Use of vacuum assisted molding was also found to be capable to fill very small gap between die and substrate of the order of 50um without voiding concerns. This paper outlines the multidisciplinary effort undertaken to design, develop, and qualify flip chip package with MUF technology for mobile application; which was successfully introduced in high volume production with yields and reliability at parity with an equivalent CUF package. MUF material with fine filler size was chosen from a material screening DOE; and was used in series of test vehicles (TVs) with different package configurations including single die and multi-die flip chip CSP packages. Process and material margin studies were conducted to establish process window for MUF technology with eutectic and Pb-free bump assemblies. Finally MUF technology was intercepted on mobile application processor product with fcTFBGA-12×12 mm sq. package and 7.5×7.5 $mm^{2}$ die towards a successful introduction into high volume production. MUF challenges as well as known-limitations are also described along with future plan. Further studies are being conducted to characterize and qualify MUF on larger die sizes and/or with finer bump pitches and to establish the process and reliability margins of MUF with the same. |
| Starting Page | 1250 |
| Ending Page | 1257 |
| File Size | 1163168 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781424464104 |
| ISSN | 05695503 |
| e-ISBN | 9781424464128 |
| e-ISBN | 9781424464111 |
| DOI | 10.1109/ECTC.2010.5490861 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-06-01 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Flip chip Assembly Costs Conducting materials Strips Chip scale packaging Production Baseband Pricing Subcontracting |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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