NDLI: Time-domain simulation of system interconnect using convolution and Newton-Raphson iteration methods

Content Provider	IEEE Xplore Digital Library
Author	Cocchini, M. Becker, W.D. Katopis, G. Pytel, S.G.
Copyright Year	2010
Description	Author affiliation: IBM STG Group, 2455 South Road Poughkeepsie, NY (Cocchini, M.; Becker, W.D.; Katopis, G.) \|\| Ansoft Corporation, 25 Burlington Mall Rd Burlington, MA (Pytel, S.G.)
Abstract	In today's world electronic system interconnections, commonly called channels, are routed over packages and printed circuit boards and are characterized by measuring eyes and calculating the bit error rate (BER). Many factors such as jitter, inter-symbol interference, simultaneous switching noise and crosstalk impact the BER of an interconnection. In the design phase, it is common practice to use circuit simulation to guarantee an acceptable BER level. This is done by acquiring the voltage waveform at the input of the receiver circuit in a robust statistical manner using time domain simulations. The possible time-domain simulation techniques can be classified in two ways: a transient solver (e.g., ASTAP, Spice) which uses non-linear Newton-Raphson iteration methods, and another second technique based on linear convolution and which has gained wide acceptance more recently due to the large number of bits that can be simulated. In this work, the two methods are applied for the timedomain analysis of a real interconnection system represented by the concatenation of 52 mixed 2-D and 3-D models. The 3D models are needed to describe the high-order modes in proximity of package discontinuities, such as via transitions and connectors. The ports of these models range in number from 18 to 36 depending on the number of aggressors that can create significant crosstalk. In this work the required rules of thumb derived from a sampling criterion will be described, so that the correct sampling frequency of the S-parameter models can be determined and robust simulation results for such a large cascaded netlist can be achieved. The overall interconnection model includes behavioral models for the driver and receiver circuits that employ equalization. Behavioral models give a needed simplification because the complexity of the original transistor-level I/O circuits leads to unacceptable long simulation times. We will use the analysis of the described real interconnection system to compare the two transient simulation approaches and quantify their expected accuracy. Furthermore, the limitations of the existing simulation methods in handling complex interconnections will be discussed, with particular emphasis on the checking and enforcement of causality and passivity for these models.
Starting Page	646
Ending Page	651
File Size	1128978
Page Count	6
File Format	PDF
ISBN	9781424464104
ISSN	05695503
e-ISBN	9781424464128
e-ISBN	9781424464111
DOI	10.1109/ECTC.2010.5490811
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Time domain analysis Convolution Circuit simulation Integrated circuit interconnections Bit error rate Crosstalk Sampling methods Electronics packaging Printed circuits Eyes
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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