NDLI: Fine pitch connection and thermal stress analysis of a novel Wafer Level Packaging technology using laminating process

Content Provider	IEEE Xplore Digital Library
Author	Okayama, Y. Nakasato, M. Saitou, K. Yanase, Y. Kobayashi, H. Yamamoto, T. Usui, R. Inoue, Y.
Copyright Year	2010
Description	Author affiliation: Advanced Devices Research Center, SANYO Electric Co., Ltd. 180 Ohmori, Anpachi-Cho, Anpachi-Gun, Gifu 503-0195, Japan (Okayama, Y.; Nakasato, M.; Saitou, K.; Yanase, Y.; Kobayashi, H.; Yamamoto, T.; Usui, R.; Inoue, Y.)
Abstract	We have been developing a novel Wafer Level Packaging technology which has a possibility of lowering WLP cost drastically by applying some JISSO techniques to WLP manufacturing processes [1]. In short, our idea is laminating a Cu wafer having Cu bumps to a Si wafer in which LSIs are formed with a nonconductive thermosetting resin. The process flow of the novel WLP technology is as follows; 1. Cu bump formation by wet etching of a Cu wafer 2. Ni/Au plating both on top of the Cu bumps and Al electrodes on Si wafer 3. NCF (Non Conductive Film) laminating to a bump side of the Cu wafer 4. Laminating (thermo compression bonding) of Cu and Si wafer after alignment 5. Re-distribution wiring formation by wet etching of the Cu wafer 6. PSR laminating, solder ball mounting, and dicing In this work, fine pitch connection (less than 100um) for the novel WLP technology has been investigated. To achieve it, there are two major issues; Cu thickness before redistribution wiring formation, and misalignment between Cu bumps and LSI electrodes. As for the Cu thickness, less than 20um is required for the fine pitch re-distribution formation, and should be more than 40um at the laminating process because of handling property (easy to convey, avoiding wrinkle or scar). To solve the mismatch of the thickness, we established a process flow in which 40–50um thick Cu is laminated with Si, Cu is wet etched down to 10–20um, then re-distribution is formed. To reduce the misalignment, we made a thermal expansion model and extracted an equation which determines an optimum offset value for any laminating conditions. By using the equation, misalignment within a wafer was reduced to less than 15um. Applying the above, good electrical connection was confirmed with fine pitch of less than 100um (60–80um). In addition, thermal stress analysis was applied to a structure of a WLP mounted on a PCB. As a result of the analysis, cumulative equivalent inelastic strain of solder ball, which connects the WLP and the PCB electrode, during temperature cycling test of our novel WLP structure was less than that of the conventional Cu post type WLP. It shows that the novel WLP structure has good stress relaxation property and board level reliability.
Starting Page	287
Ending Page	292
File Size	1033327
Page Count	6
File Format	PDF
ISBN	9781424464104
ISSN	05695503
e-ISBN	9781424464128
e-ISBN	9781424464111
DOI	10.1109/ECTC.2010.5490960
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Thermal stresses Wafer scale integration Wet etching Electrodes Wiring Equations Costs Manufacturing processes Resins Gold
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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