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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Qwai Low Osenbach, J. YongSeok Yang KyeongSool Seong SeokHo Na |
| Copyright Year | 2010 |
| Description | Author affiliation: LSI Corporation USA (Qwai Low; Osenbach, J.) || Amkor Technology Korea (YongSeok Yang; KyeongSool Seong; SeokHo Na) |
| Abstract | Results of a development program aimed at introducing Cu wire to a low K circuit under pad integrated circuit made in 65nm technology are summarized. The results demonstrate that if the wire bond process is optimized along with the tool design, then it is possible to produce both substrate (PBGA) and lead frame (TQFP) devices with pure Cu wire that show no evidence of damage to the underlining dielectric stack, robust ball bonds and stitch bonds with no evidence of lifts or cracks. Furthermore, the data demonstrate that the fundamental reliability of both packages as determined by temperature cycling, high temperature humidity storage and high temperature storage is more than sufficient if the correct mold compound is used. |
| Starting Page | 1154 |
| Ending Page | 1158 |
| File Size | 941482 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424464104 |
| ISSN | 05695503 |
| e-ISBN | 9781424464128 |
| e-ISBN | 9781424464111 |
| DOI | 10.1109/ECTC.2010.5490847 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-06-01 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Wire Bonding Silicon Temperature Dielectric substrates Integrated circuit technology Design optimization Lead Dielectric devices Robustness |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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